JP-UM-A-5-36544 (Patent Document 1; page 2, FIG. 1) discloses a microcomputer control device comprising a microcomputer for outputting a control signal to control a predetermined load, a watchdog circuit for detecting an abnormal operation state of the microcomputer and outputting a reset signal to reset the microcomputer, a fail safe circuit for outputting a fail safe signal in response to the reset signal of the watchdog circuit, and a signal switching circuit for switching the control signal of the microcomputer to the fail safe side in response to the fail safe signal.
However, this microcomputer control device disclosed in the Patent Document 1 is insufficient for systems such as ABS, VSC, etc., because merely monitoring a watchdog pulse is not enough. Higher-level monitoring (in which a command is accurately executed, etc.) is needed.
Using two microcomputers for executing a function check while carrying out mutual data communication therebetween and comparing the check results does not effectively solve this problem because the costs become too high, thereby weakening the competitiveness of the final products.